1. Field of the Invention
The present invention relates to a semiconductor device and a formation method thereof, and more particularly, to a semiconductor device and a method of fabricating the same, in which has an epitaxial layer for controlling a threshold voltage.
2. Description of the Related Art
In general, various ion implantations are processed for embodying electric property of a MOS-transistor. Ion implantation is a process wherein impurity atoms are ionized and accelerated in an electric field to be implanted into a wafer, for the sake of substituting an impurity doping process by a high-temperature diffusion in a semiconductor device.
Ion implantation is both to control a dose of the impurity accurately and to control a distribution shape of the implanted ions. Additionally, Ion implantation has advantages that a lateral spread phenomenon is reduced in contrast to the high-temperature diffusion and a uniformity of impurity concentration in the wafer is excellent.
Ion implantation is used for threshold voltage control, punch through prevention, well formation, or isolation of circuit elements, etc., in MOS (Metal Oxide Semiconductor) transistors, and also for resistor formation, base formation, and isolation of devices, etc., in bipolar transistors.
However, the ions injected in the ion implantation apparatus are collided with a wafer, which can induce strains and defects. In order to overcome such problems, an annealing process is generally performed.
On the other hand, the semiconductor device generally comprises various electronic elements, such as transistors and capacitors formed on the semiconductor substrate, and wires that connect them with each other. To integrate such elements on the semiconductor substrate, it preferentially needs to isolate electrically regions where various electronic elements are formed, which is so-called “a device isolation.”
LOCOS (Local Oxidation of Silicon) method, widely known as an isolation technique, involves forming an isolating oxide film on a field area to electrically isolate device active areas. However, a bird's beak phenomenon in the field area may occur. Namely, peripheral portions of the isolating oxide film may spread to reduce the active areas where circuit elements will be formed, thus resulting in decreasing a channel length and a punch through.
Recently, a STI (Shallow Trench Isolation) technique has been widely used to solve these problems. Advantages of the STI technique are both to minimize formation areas of dielectric films and to form a stable isolation structure. To explain isolation method using the STI technique, a silicon nitride film is firstly deposited on a semiconductor substrate on which an oxide thin film is previously formed, and it is patterned. Next, using the silicon nitride film as an etch-mask, the semiconductor substrate is etched to form a trench. After that, a liner oxide film is formed inside of the trench, and then the trench is sufficiently filled with a silicon oxide material. CMP (Chemical Mechanical Polishing) process is performed to planarize the patterned silicon nitride film until a surface thereof is exposed. Therefore, active areas in the semiconductor substrate are isolated by the silicon oxide film. For following processes in the isolated state, the patterned silicon nitride film remaining in the active area is removed.
However, there are such problems as the liner oxide film may be etched during a cleaning process prior to fabrication of a gate dielectric film. Moreover, a moat phenomenon, in which a STI gap-fill oxide film is etched, can also occur.